Module Definition
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Module : dti_mux21
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 100.00 66.67 100.00

Source File(s) :
/nfs_project/gemini/DV/nadeem/dv/main_regression_21-10-2022/gemini/design/mem_ss/ddr_ss/../../ip/dti/libs/dti_tm16_phy/hdl/library/dti_tm16ffc_16f96_9t_stdcells_rev1p0p0_pwr.v

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst34.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst46.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst47.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst52.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst58.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst59.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst96.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst102.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst105.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst107.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst140.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst159.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst164.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst166.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst227.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst234.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst235.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst244.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst251.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst255.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst257.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst274.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst276.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst280.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst304.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst312.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst318.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst322.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst325.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst347.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst353.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst356.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst358.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst359.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst375.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst381.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst384.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst392.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst400.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst406.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst411.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst438.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst451.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst468.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst510.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst540.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst552.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst566.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst599.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst606.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst615.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst627.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst651.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst657.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst661.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst672.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst699.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst715.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst717.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst718.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst732.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst747.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst754.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst782.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst805.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst822.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst862.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst864.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst901.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst924.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst928.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst945.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst958.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst961.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst962.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst973.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst977.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1011.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1031.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1037.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1072.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1103.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1104.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1121.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1124.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1127.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1166.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1173.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1175.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1190.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1197.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1206.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1226.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1231.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1237.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1248.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1263.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1281.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1289.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1324.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1338.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1345.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1363.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1368.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1370.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1417.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1422.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1424.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1430.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1438.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1455.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1478.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1482.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1489.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1500.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1508.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1516.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1548.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1555.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1575.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1584.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1586.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1596.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1599.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1605.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1623.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1630.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1640.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1646.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1663.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1667.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1695.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1699.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1700.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1717.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1718.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1746.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1754.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1757.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1777.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1801.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1829.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1853.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1865.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1881.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1886.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1890.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1916.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1932.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1933.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1938.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1952.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1958.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1973.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1974.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1985.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1986.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1991.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2014.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2055.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2059.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2075.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2093.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2094.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2144.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2155.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2204.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2216.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2221.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2222.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2223.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2232.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2250.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2285.xdti_16f_9t_96_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2306.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2309.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2314.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2392.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2415.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2424.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2426.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2431.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2451.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2456.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2464.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2469.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2477.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2480.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2502.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2503.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2505.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2575.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2582.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2595.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2649.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2697.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2705.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2713.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2716.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2726.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2744.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2768.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2774.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2778.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2791.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2812.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2839.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2870.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2871.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2881.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2889.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2960.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2963.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2985.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2993.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3003.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3025.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3031.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3034.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3050.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3093.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3110.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3132.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3169.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3170.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3177.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3181.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3201.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3212.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3226.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3235.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3280.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3327.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3336.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3346.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3371.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3372.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3390.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3411.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3414.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3415.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3416.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3421.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3424.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3463.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3466.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3471.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3505.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3544.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3545.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3546.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3573.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3579.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3590.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3619.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3642.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3678.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3686.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3710.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3715.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3759.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3769.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3770.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3787.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3789.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3790.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3794.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3797.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3814.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3817.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3824.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3832.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3862.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3863.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3870.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3871.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3905.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3916.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3924.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3933.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3949.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3954.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3972.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3975.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3977.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3986.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3999.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4009.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4011.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4043.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4046.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4048.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4052.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4056.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4063.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4066.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4072.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4076.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4080.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4102.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4106.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4116.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4127.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4181.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4201.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4228.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4240.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4243.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4244.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4264.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4279.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4288.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4295.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4302.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4318.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4351.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4356.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4359.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4375.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4418.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4438.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4468.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4471.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4486.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4549.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4572.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4587.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4598.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4601.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4616.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4621.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4625.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4626.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4650.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4700.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4708.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4762.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4775.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4808.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4810.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4811.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4812.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4815.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4839.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4843.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4847.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4850.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4885.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4887.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4897.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4913.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4925.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4928.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4931.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4946.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4955.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4962.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4965.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4985.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4993.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4994.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5005.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5024.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5038.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5074.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5080.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5097.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5148.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5152.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5161.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5168.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5181.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5190.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5191.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5193.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5218.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5219.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5268.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5278.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5283.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5286.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5298.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5299.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5309.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5330.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5345.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5360.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5365.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5378.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5383.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5388.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5396.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5400.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5404.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5410.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5412.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5446.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5458.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5471.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5481.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5488.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5495.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5530.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5566.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5572.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5586.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5596.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5605.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5608.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5623.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5646.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5652.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5667.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5674.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5690.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5704.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5740.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5741.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5747.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5752.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5766.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5799.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5824.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5827.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5845.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5851.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5898.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5902.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5904.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5916.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5921.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5939.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5953.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5959.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5962.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6001.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6024.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6038.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6072.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6089.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6099.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6104.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6121.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6124.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6131.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6146.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6178.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6180.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6239.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6250.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6300.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6306.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6311.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6331.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6347.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6348.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6354.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6362.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6374.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6428.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6450.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6479.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6482.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6490.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6504.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6505.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6528.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6529.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6533.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6536.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6543.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6549.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6572.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6584.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6591.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6605.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6647.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6705.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6707.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6816.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6817.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6818.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6846.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6853.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6860.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6874.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6877.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6913.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6936.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6944.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6957.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6963.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6981.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7012.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7017.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7025.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7035.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7047.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7077.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7080.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7099.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7108.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7133.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7141.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7144.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7156.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7165.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7167.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7178.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7201.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7236.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7266.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7276.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7299.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7304.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7306.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7313.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7332.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7357.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7361.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7365.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7374.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7378.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7385.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7396.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7409.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7414.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7425.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7434.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7443.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7458.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7485.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7504.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7518.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7519.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7528.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7536.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7550.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7568.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7619.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7651.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7660.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7704.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7732.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7739.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7763.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7780.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7801.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7819.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7839.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7853.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7854.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7879.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7880.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7890.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7893.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7896.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7918.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7975.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7981.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8003.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8007.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8028.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8039.xdti_16f_9t_96_ckmux21.xmux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8041.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8043.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8063.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8065.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8069.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8072.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8075.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8124.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8125.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8150.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8155.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8170.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8185.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8195.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8220.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8244.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8253.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8305.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8325.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8366.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8387.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8406.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8409.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8421.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8449.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8458.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8485.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8486.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8492.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8512.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8518.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8534.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8537.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8549.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8559.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8586.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8597.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8599.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8608.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8615.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8621.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8636.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8638.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8647.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8661.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8683.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8684.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8718.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8720.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8738.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8776.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8801.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8803.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8856.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8869.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8870.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8886.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8891.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8905.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8915.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8917.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8923.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8925.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8937.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8938.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8941.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8951.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8955.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8968.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8979.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8984.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9000.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9003.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9014.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9024.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9050.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9053.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9059.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9071.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9075.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9079.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9088.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9094.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9104.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9130.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9135.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9160.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9171.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9172.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9199.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9203.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9213.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9214.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9219.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9230.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9253.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9256.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9279.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9344.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9353.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9384.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9388.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9395.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9396.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9406.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9423.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9424.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9429.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9445.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9458.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9470.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9471.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9475.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9479.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9510.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9516.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9518.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9522.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9541.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9551.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9565.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9567.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9571.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9575.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9605.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9631.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9655.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9659.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9672.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9699.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9703.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9715.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9723.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9756.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9768.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9788.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9819.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9825.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9860.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9890.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9892.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9901.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9906.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9908.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9909.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9914.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9925.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9927.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9929.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9938.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9944.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9948.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9957.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9969.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9980.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9993.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10001.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10003.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10018.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10026.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10035.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10037.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10042.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10043.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10094.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10098.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10120.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10128.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10134.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10155.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10168.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10187.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10205.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10212.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10213.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10225.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10250.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10259.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10278.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10291.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10302.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10313.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10332.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10355.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10371.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10377.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10379.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10380.xdti_16f_9t_96_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10396.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10397.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10428.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10465.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10470.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10478.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10486.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10495.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10545.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10546.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10559.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10563.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10574.xdti_16f_9t_96_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10575.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10583.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10605.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10611.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10621.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10637.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10639.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10643.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10644.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10647.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10655.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10661.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10668.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10677.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10688.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10704.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10712.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10717.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10724.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10728.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10735.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10748.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10800.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10802.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10807.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10813.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10824.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10856.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10857.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10875.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10876.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10881.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10889.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10899.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10940.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10985.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11025.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11031.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11042.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11051.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11052.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11053.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11064.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11071.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11073.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11075.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11096.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11102.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11125.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11126.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11143.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11158.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11192.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11201.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11203.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11211.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11228.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11236.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11240.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11244.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11259.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11276.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11291.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11295.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11296.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11300.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11303.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11318.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11320.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11345.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11355.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11365.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11374.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11396.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11402.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11405.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11437.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11441.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11444.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11478.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11499.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11514.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11523.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11526.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11527.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11529.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11538.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11545.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11549.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11573.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11585.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11586.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11597.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11600.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11614.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11618.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11676.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11688.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11701.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11704.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11711.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11724.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11763.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11767.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11775.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11784.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11785.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11789.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11802.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11803.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11810.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11821.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11824.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11825.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11836.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11846.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11854.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11881.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11885.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11888.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11911.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11914.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11931.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11986.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11988.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12007.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12042.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12054.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12058.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12064.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12070.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12085.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12087.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12103.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12111.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12140.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12149.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12175.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12193.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12195.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12227.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12244.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12245.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12288.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12313.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12323.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12363.xdti_16f_9t_96_ckmux21.xmux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12370.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12371.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12375.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12406.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12479.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12505.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12528.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12551.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12559.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12577.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12597.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12611.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12676.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12679.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12714.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12720.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12736.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12737.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12740.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12741.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12771.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12772.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12785.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12786.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12810.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12825.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12827.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12828.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12847.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12852.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12860.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12881.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12887.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12910.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12934.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12980.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12996.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13000.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13011.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13014.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13019.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13024.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13030.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13040.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13048.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13066.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13070.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13074.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13104.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13117.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13137.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13152.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13168.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13200.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13205.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13213.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13229.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13284.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13285.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13294.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13316.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13329.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13330.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13343.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13346.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13354.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13357.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13364.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13382.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13384.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13392.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13394.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13406.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13410.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13458.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13505.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13537.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13545.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13573.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13595.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13596.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13598.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13618.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13619.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13622.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13633.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13643.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13648.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13657.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13658.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13673.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13699.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13700.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13705.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13709.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13710.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13718.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13727.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13734.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13752.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13758.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13761.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13778.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13790.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13800.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13806.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13842.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13844.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13846.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13869.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13893.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13905.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13913.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13918.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13923.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13934.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13947.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13952.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13953.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14008.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14010.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14026.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14030.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14039.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14059.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14073.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14122.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14128.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14151.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14170.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14175.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14182.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14197.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14224.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14225.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14226.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14249.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14265.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14281.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14291.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14297.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14307.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14329.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14334.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14356.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14360.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14362.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14407.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14430.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14492.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14502.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14540.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14569.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14575.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14614.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14629.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14638.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14694.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14703.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14715.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14735.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14740.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14767.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14782.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14792.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14817.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14818.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14822.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14826.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14848.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14857.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14859.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14880.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14893.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14899.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14917.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14938.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14945.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14950.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14973.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15013.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15028.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15084.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15085.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15100.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15124.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15136.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15137.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15140.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15144.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15158.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15168.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15178.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15186.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15190.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15199.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15205.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15221.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15272.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15273.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15284.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15296.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15321.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15335.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15346.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15351.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15380.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15395.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15410.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15438.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15452.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15464.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15494.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15513.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15534.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15535.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15537.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15586.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15594.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15619.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15620.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15643.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15645.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15657.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15662.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15669.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15672.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15686.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15691.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15697.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15699.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15706.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15754.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15763.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15784.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15787.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15791.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15854.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15865.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15916.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15927.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15935.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15942.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15948.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15951.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15956.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15960.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16006.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16035.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16052.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16055.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16066.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16084.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16089.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16094.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16099.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16125.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16219.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16230.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16238.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16278.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16289.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16303.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16305.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16341.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16342.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16366.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16381.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16382.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16395.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16397.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16408.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16441.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16471.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16473.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16478.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16482.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16493.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16497.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16502.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16528.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16541.xdti_16f_9t_96_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16582.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16596.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16608.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16617.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16618.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16664.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16667.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16679.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16680.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16685.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16686.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16707.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16720.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16724.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16725.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16728.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16732.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16733.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16768.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16772.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16787.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16808.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16819.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16826.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16840.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16842.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16853.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16868.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16889.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16890.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16902.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16903.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16905.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16906.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16913.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16919.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16926.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16956.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17015.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17019.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17035.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17067.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17072.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17079.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17084.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17086.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17118.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17127.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17137.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17140.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17145.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17151.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17169.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17171.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17188.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17203.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17214.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17229.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17232.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17236.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17237.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17238.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17258.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17303.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17307.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17318.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17349.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17358.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17362.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17369.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17370.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17371.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17390.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17391.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17392.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17422.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17443.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17445.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17453.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17455.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17463.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17465.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17466.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17469.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17484.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17510.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17531.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17536.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17541.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17571.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17607.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17615.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17634.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17640.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17686.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17687.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17690.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17711.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17736.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17747.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17756.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17771.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17800.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17862.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17864.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17870.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17882.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17895.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17896.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17898.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17903.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17907.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17911.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17933.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17949.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17950.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17958.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17961.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18002.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18018.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18023.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18027.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18032.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18046.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18054.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18071.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18132.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18145.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18170.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18191.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18209.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18214.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18233.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18237.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18243.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18257.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18291.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18295.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18308.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18340.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18354.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18355.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18365.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18390.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18441.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18444.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18455.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18484.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18489.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18495.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18508.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18515.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18517.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18535.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18557.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18604.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18607.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18613.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18615.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18621.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18631.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18635.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18660.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18670.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18672.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18708.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18732.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18743.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18745.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18756.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18762.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18765.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18772.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18788.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18796.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18803.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18805.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18816.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18820.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18845.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18898.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18918.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18926.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18927.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18938.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18951.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18965.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18977.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18988.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18991.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18994.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19010.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19012.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19013.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19014.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19016.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19022.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19032.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19058.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19063.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19068.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19078.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19083.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19085.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19101.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19108.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19114.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19122.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19124.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19138.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19146.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19156.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19166.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19171.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19180.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19184.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19186.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19193.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19212.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19219.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19227.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19235.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19236.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19254.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19270.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19274.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19283.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19304.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19330.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19360.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19362.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19375.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19382.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19388.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19396.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19400.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19409.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19410.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19440.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19446.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19463.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19468.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19477.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19478.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19489.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19494.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19511.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19517.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19527.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19530.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19547.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19551.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19552.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19575.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19588.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19592.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19596.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19605.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19614.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19622.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19635.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19662.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19678.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19683.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19686.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19714.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19718.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19726.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19802.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19803.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19812.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19820.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19828.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19863.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19892.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19894.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19895.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19921.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19955.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19976.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19993.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20012.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20038.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20068.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20092.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20107.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20156.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20166.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20191.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20197.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20206.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20222.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20229.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20234.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20239.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20243.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20281.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20283.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20284.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20285.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20286.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20297.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20302.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20316.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20330.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20348.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20351.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20359.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20360.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20362.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20381.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20387.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20392.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20396.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20405.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20411.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20412.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20451.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20482.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20536.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20559.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20563.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20565.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20569.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20570.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20577.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20587.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20590.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20597.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20607.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20611.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20617.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20648.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20656.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20681.xdti_16f_9t_96_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20694.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20702.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20705.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20710.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20768.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20774.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20775.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20785.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20792.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20803.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20804.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20810.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20820.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20842.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20854.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20866.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20872.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20874.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20879.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20891.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20901.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20920.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20941.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20959.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20976.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21005.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21024.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21034.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21038.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21040.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21044.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21052.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21060.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21071.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21073.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21075.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21115.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21116.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21118.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21125.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21134.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21135.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21164.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21173.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21175.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21177.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21184.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21196.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21204.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21207.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21226.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21266.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21278.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21281.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21286.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21298.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21306.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21322.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21324.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21329.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21333.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21360.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21396.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21402.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21421.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21439.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21462.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21465.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21467.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21475.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21496.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21526.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21534.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21587.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21626.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21627.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21640.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21646.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21662.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21663.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21680.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21702.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21711.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21753.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21763.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21778.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21784.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21786.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21797.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21802.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21821.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21836.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21841.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21845.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21855.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21857.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21858.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21861.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21864.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21897.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21903.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21956.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21965.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21983.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22003.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22010.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22011.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22035.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22038.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22048.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22057.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22061.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22096.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22104.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22109.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22142.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22146.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22213.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22219.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22228.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22242.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22247.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22262.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22272.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22313.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22317.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22324.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22329.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22340.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22341.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22346.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22356.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22380.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22387.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22405.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22411.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22436.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22449.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22467.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22511.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22528.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22535.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22544.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22550.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22585.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22587.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22588.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22638.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22655.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22663.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22668.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22670.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22673.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22689.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22702.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22703.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22733.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22741.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22742.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22762.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22773.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22795.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22817.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22821.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22825.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22830.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22841.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22856.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22874.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22885.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22888.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22898.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22905.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22907.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22927.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22928.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22933.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22938.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22940.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22974.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22997.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23004.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23039.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23055.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23057.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23060.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23069.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23108.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23111.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23113.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23133.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23139.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23150.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23161.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23184.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23194.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23195.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23212.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23241.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23269.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23273.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23276.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23285.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23288.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23289.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23291.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23294.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23332.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23335.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23352.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23365.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23396.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23397.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23401.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23404.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23405.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23418.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23445.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23470.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23496.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23502.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23518.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23525.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23539.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23541.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23551.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23554.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23555.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23556.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23563.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23570.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23573.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23579.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23587.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23591.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23626.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23649.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23673.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23688.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23707.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23712.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23713.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23718.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23720.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23742.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23756.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23769.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23772.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23790.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23791.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23797.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23800.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23806.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23807.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23872.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23877.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23899.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23903.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23913.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23923.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23937.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23964.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24000.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24003.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24018.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24023.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24030.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24044.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24054.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24056.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24109.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24123.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24129.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24136.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24173.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24188.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24210.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24223.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24227.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24233.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24287.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24300.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24306.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24322.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24332.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24357.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24369.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24383.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24397.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24412.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24421.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24435.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24436.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24437.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24444.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24460.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24468.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24471.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24489.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24490.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24512.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24530.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24538.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24553.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24565.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24571.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24601.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24634.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24641.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24642.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24661.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24676.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24691.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24714.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24758.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24789.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24796.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24797.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24801.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24818.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24821.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24847.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24873.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24895.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24905.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24913.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24918.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24933.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24950.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24986.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25005.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25022.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25034.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25039.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25041.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25055.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25074.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25086.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25087.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25097.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25110.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25112.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25114.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25119.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25125.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25134.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25137.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25145.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25149.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25156.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25174.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25220.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25226.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25239.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25241.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25243.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25247.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25252.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25266.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25275.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25276.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25278.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25288.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25297.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25314.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25315.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25320.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25327.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25342.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25364.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25367.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25384.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25439.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25444.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25452.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25467.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25468.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25480.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25534.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25535.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25549.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25586.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25605.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25612.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25616.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25628.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25629.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25633.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25639.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25669.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25690.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25733.xdti_16f_9t_96_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25743.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25746.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25751.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25752.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25761.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25765.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25777.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25784.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25787.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25798.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25801.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25834.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25835.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25873.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25891.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25942.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25946.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25961.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25969.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25996.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25997.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26000.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26011.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26017.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26042.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26053.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26078.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26080.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26089.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26105.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26126.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26134.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26149.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26188.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26194.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26198.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26199.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26204.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26216.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26220.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26226.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26245.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26254.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26256.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26260.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26266.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26270.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26303.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26312.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26317.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26321.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26323.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26356.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26357.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26370.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26373.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26423.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26424.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26426.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26434.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26436.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26442.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26452.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26458.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26470.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26490.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26513.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26529.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26534.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26540.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26560.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26575.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26576.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26584.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26631.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26643.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26660.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26668.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26706.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26726.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26735.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26763.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26782.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26805.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26813.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26818.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26824.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26859.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26879.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26889.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26895.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26896.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26904.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26906.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26933.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26946.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26959.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26973.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26981.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27013.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27023.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27024.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27053.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27058.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27085.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27088.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27106.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27108.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27114.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27126.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27155.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27190.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27202.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27239.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27259.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27266.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27272.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27294.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27312.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27321.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27340.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27364.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27365.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27368.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27390.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27424.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27425.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27431.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27432.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27455.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27462.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27467.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27494.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27495.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27512.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27515.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27519.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27541.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27549.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27570.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27572.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27586.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27622.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27658.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27660.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27687.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27705.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27720.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27724.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27726.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27735.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27756.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27804.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27807.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27814.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27820.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27834.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27839.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27840.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27880.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27884.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27888.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27908.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27926.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27934.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27952.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27997.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28034.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28038.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28046.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28047.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28069.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28074.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28084.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28092.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28093.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28112.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28117.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28149.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28154.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28189.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28203.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28236.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28256.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28297.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28303.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28308.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28315.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28333.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28348.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28361.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28368.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28374.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28377.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28380.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28408.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28411.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28423.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28442.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28445.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28485.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28495.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28518.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28523.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28544.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28560.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28567.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28582.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28587.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28627.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28633.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28652.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28669.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28681.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28687.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28688.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28705.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28742.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28745.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28767.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28768.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28874.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28875.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28888.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28893.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28908.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28920.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28951.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28972.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28973.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28979.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28989.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29012.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29027.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29053.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29085.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29101.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29121.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29126.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29140.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29146.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29168.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29175.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29183.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29216.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29243.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29247.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29258.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29268.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29277.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29292.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29300.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29309.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29312.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29325.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29369.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29372.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29377.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29389.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29393.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29423.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29431.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29451.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29452.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29466.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29498.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29500.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29533.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29543.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29548.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29551.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29554.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29559.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29574.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29631.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29701.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29739.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29775.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29778.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29780.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29788.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29819.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29861.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29862.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29866.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29869.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29920.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29968.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29971.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29986.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29988.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30003.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30025.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30026.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30027.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30055.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30063.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30071.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30106.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30150.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30173.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30198.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30203.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30230.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30239.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30265.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30281.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30284.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30287.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30288.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30299.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30318.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30322.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30324.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30330.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30338.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30371.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30387.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30390.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30405.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30412.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30417.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30420.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30434.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30437.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30445.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30473.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30475.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30480.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30481.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30485.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30502.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30539.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30564.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30625.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30641.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30646.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30729.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30733.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30750.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30779.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30799.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30820.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30826.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst24.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst26.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst27.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst28.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst31.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst42.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst62.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst80.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst89.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst90.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst96.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst97.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst103.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst105.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst109.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst119.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst128.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst135.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst136.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst142.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst152.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst157.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst163.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst171.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst177.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst198.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst206.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst219.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst222.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst228.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst242.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst251.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst252.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst266.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst295.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst299.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst306.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst314.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst317.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst322.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst334.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst353.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst359.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst396.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst403.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst420.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst421.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst437.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst469.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst472.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst475.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst482.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst498.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst513.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst519.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst547.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst556.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst563.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst568.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst578.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst587.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst598.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst601.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst604.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst610.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst618.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst637.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst657.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst663.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst667.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst698.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst699.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst705.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst715.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst729.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst737.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst759.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst775.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst778.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst784.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst798.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst819.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst820.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst827.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst836.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst843.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst850.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst866.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst873.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst874.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst878.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst880.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst884.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst892.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst934.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst936.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst949.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst969.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst982.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst983.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst986.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst991.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst999.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1018.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1023.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1024.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1028.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1029.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1030.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1031.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1046.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1055.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1056.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1057.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1060.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1079.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1092.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1094.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1106.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1120.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1171.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1183.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1208.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1209.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1227.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1239.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1252.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1253.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1298.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1301.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1302.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1307.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1327.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1342.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1349.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1353.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1355.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1360.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1372.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1421.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1423.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1426.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1454.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1456.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1480.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1506.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1508.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1522.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1529.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1542.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1552.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1564.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1576.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1582.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1616.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1627.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1638.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1644.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1653.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1684.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1689.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1693.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1694.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1722.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1727.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1728.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1737.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1741.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1761.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1767.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1771.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1773.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1779.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1791.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1792.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1817.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1820.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1823.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1824.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1830.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1837.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1847.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1849.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1861.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1884.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1916.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1923.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1929.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1936.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1946.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1953.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1956.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1963.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1989.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2002.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2016.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2024.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2041.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2066.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2088.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2094.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2098.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2102.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2103.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2107.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2110.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2112.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2131.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2133.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2141.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2148.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2153.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2172.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2174.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2185.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2194.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2196.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2205.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2216.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2218.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2220.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2223.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2233.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2240.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2250.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2261.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2263.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2273.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2279.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2283.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2291.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2300.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2312.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2330.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2332.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2338.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2342.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2346.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2360.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2364.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2377.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2385.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2386.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2387.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2393.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2400.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2427.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2430.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2449.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2481.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2482.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2497.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2510.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2511.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2530.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2533.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2538.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2541.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2543.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2593.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2594.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2602.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2604.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2617.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2634.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2661.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2665.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2713.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2718.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2738.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2739.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2741.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2749.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2753.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2758.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2761.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2770.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2789.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2790.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2795.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2824.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2843.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2845.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2870.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2877.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2888.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2918.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2920.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2924.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2963.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2964.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2972.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2995.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3018.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3034.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3054.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3057.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3070.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3076.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3136.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3142.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3145.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3164.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3172.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3180.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3193.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3201.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3203.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3245.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3247.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3256.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3259.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3261.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3298.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3311.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3317.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3318.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3323.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3334.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3336.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3354.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3375.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3376.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3401.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3404.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3408.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3416.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3426.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3428.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3435.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3439.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3455.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3467.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3489.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3503.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3516.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3519.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3526.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3527.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3533.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3536.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3540.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3546.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3547.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3570.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3572.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3595.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3596.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3603.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3605.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3606.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3608.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3612.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3634.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3644.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3657.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3664.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3670.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3690.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3695.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3696.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3718.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3725.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3727.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3749.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3761.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3762.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3769.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3770.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3780.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3784.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3785.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3789.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3847.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3858.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3860.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3866.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3888.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3895.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3900.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3902.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3916.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3923.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3931.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3933.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3947.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3986.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3990.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3994.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4004.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4016.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4026.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4038.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4043.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4060.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4062.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4077.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4085.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4086.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4108.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4132.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4136.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4153.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4155.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4185.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4186.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4187.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4192.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4194.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4198.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4203.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4204.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4219.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4223.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4225.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4248.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4250.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4256.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4274.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4294.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4306.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4310.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4314.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4334.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4381.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4387.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4395.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4400.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4402.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4421.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4422.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4423.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4455.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4470.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4524.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4531.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4539.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4555.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4561.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4569.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4571.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4576.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4582.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4613.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4617.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4666.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4669.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4675.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4686.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4704.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4706.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4745.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4755.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4780.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4784.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4800.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4815.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4816.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4832.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4850.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4855.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4864.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4891.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4895.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4901.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4902.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4916.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4922.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4937.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4946.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4947.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4959.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4974.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4976.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4983.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4992.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4995.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5005.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5020.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5022.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5041.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5042.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5046.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5047.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5114.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5137.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5148.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5160.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5177.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5182.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5185.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5198.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5206.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5230.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5235.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5238.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5265.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5291.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5297.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5311.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5317.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5325.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5330.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5347.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5349.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5365.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5367.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5377.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5390.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5400.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5405.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5418.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5438.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5449.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5469.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5470.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5473.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5488.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5492.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5493.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5499.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5530.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5535.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5547.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5566.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5570.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5576.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5581.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5588.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5592.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5598.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5611.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5635.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5639.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5640.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5644.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5664.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5676.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5678.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5679.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5687.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5707.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5710.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5712.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5714.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5737.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5757.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5762.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5770.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5776.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5779.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5781.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5788.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5797.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5832.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5838.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5856.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5859.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5861.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5864.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5888.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5896.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5900.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5925.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5930.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5940.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5948.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5956.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5987.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5994.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6012.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6049.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6066.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6087.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6108.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6110.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6162.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6169.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6190.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6196.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6224.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6227.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6229.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6235.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6252.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6255.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6264.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6268.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6272.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6273.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6307.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6323.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6332.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6365.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6367.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6368.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6372.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6385.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6387.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6393.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6394.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6396.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6400.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6414.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6421.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6424.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6443.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6459.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6465.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6474.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6476.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6478.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6480.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6481.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6497.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6537.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6538.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6539.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6540.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6541.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6553.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6565.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6590.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6592.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6598.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6600.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6612.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6628.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6630.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6641.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6643.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6649.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6660.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6661.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6668.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6680.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6688.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6701.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6720.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6734.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6735.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6765.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6767.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6780.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6786.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6805.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6811.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6826.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6837.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6839.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6863.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6870.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6877.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6879.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6882.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6883.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6897.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6902.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6910.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6911.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6938.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6942.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6949.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6958.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6962.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6972.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6975.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6976.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6988.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7009.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7010.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7020.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7021.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7026.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7038.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7055.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7060.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7064.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7084.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7085.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7086.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7088.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7091.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7126.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7144.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7160.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7163.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7178.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7187.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7189.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7219.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7226.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7232.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7233.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7242.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7252.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7254.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7264.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7266.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7304.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7355.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7369.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7370.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7371.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7373.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7375.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7382.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7390.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7437.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7442.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7449.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7459.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7471.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7489.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7499.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7529.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7547.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7551.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7597.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7611.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7621.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7643.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7647.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7660.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7661.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7669.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7671.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7684.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7687.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7689.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7695.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7712.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7720.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7729.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7742.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7743.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7745.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7746.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7757.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7759.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7766.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7770.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7809.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7815.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7836.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7865.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7868.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7881.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7899.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7911.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7953.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7958.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7985.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7988.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7996.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7999.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8001.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8012.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8016.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8030.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8032.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8034.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8039.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8058.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8067.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8083.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8086.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8091.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8111.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8128.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8150.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8179.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8182.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8185.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8190.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8200.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8219.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8225.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8230.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8247.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8249.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8256.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8269.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8271.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8280.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8282.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8295.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8301.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8322.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8331.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8332.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8353.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8354.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8356.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8359.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8389.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8395.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8400.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8405.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8420.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8428.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8436.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8439.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8452.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8456.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8457.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8470.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8494.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8512.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8513.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8542.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8551.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8552.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8557.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8573.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8607.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8619.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8623.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8628.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8630.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8642.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8648.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8652.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8660.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8661.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8675.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8705.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8717.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8722.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8732.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8736.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8739.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8774.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8800.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8801.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8802.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8816.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8833.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8839.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8855.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8893.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8898.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8904.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8907.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8914.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8917.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8922.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8932.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8940.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8957.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8979.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9005.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9007.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9016.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9018.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9021.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9026.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9036.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9050.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9060.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9071.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9089.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9098.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9136.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9148.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9152.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9160.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9178.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9180.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9207.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9231.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9260.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9262.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9264.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9267.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9317.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9326.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9335.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9352.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9386.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9398.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9409.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9424.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9437.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9443.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9450.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9452.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9455.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9474.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9475.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9479.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9487.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9498.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9515.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9526.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9529.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9533.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9543.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9544.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9555.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9559.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9593.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9597.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9600.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9620.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9627.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9630.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9631.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9638.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9646.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9648.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9651.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9652.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9673.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9680.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9684.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9709.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9716.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9728.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9730.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9753.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9761.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9764.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9765.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9767.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9769.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9785.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9801.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9813.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9818.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9859.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9869.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9879.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9882.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9885.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9892.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9902.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9927.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9928.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9929.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9934.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9939.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9940.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9941.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9954.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9992.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9999.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10027.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10086.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10087.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10106.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10109.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10143.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10145.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10158.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10177.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10181.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10182.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10191.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10216.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10217.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10221.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10224.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10251.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10260.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10266.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10286.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10291.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10295.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10307.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10318.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10348.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10367.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10372.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10378.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10390.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10393.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10410.xdti_16f_9t_96_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10423.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10436.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10441.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10446.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10459.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10465.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10472.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10473.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10475.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10497.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10500.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10508.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10519.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10521.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10547.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10555.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10562.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10583.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10584.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10599.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10617.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10643.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10655.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10664.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10665.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10673.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10698.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10717.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10726.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10730.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10740.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10751.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10756.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10778.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10803.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10804.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10805.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10818.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10826.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10831.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10840.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10843.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10851.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10867.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10869.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10881.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10900.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10920.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10921.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10925.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10932.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10937.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10939.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10950.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10953.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10957.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10978.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10980.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10982.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10989.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11000.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11003.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11011.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11054.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11059.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11065.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11072.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11081.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11095.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11101.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11111.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11112.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11115.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11124.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11155.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11156.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11163.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11166.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11176.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11190.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11199.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11216.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11217.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11221.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11225.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11250.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11256.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11278.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11289.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11304.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11317.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11380.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11402.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11407.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11431.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11439.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11458.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11464.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11479.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11486.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11500.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11501.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11502.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11509.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11512.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11536.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11581.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11595.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11603.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11643.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11647.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11650.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11662.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11668.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11670.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11691.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11719.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11735.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11762.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11786.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11789.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11806.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11820.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11822.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11833.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11840.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11842.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11858.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11890.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11895.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11922.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11943.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11951.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11978.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11979.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11982.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11992.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12038.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12042.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12079.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12080.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12096.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12117.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12121.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12133.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12135.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12137.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12147.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12149.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12154.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12157.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12195.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12202.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12235.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12236.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12241.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12267.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12278.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12279.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12281.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12286.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12289.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12303.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12306.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12310.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12330.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12343.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12364.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12378.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12403.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12415.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12419.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12442.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12445.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12446.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12449.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12454.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12456.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12466.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12489.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12490.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12497.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12498.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12541.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12567.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12571.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12572.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12581.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12597.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12613.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12638.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12661.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12663.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12696.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12699.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12706.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12738.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12744.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12749.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12750.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12765.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12766.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12772.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12786.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12789.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12796.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12809.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12810.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12813.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12818.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12835.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12876.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12883.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12900.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12907.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12916.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12928.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12946.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12962.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12970.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12982.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12983.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12998.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13034.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13037.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13061.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13070.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13072.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13089.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13101.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13118.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13131.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13139.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13141.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13157.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13178.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13180.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13187.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13191.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13194.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13201.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13202.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13211.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13231.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13238.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13249.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13253.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13259.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13281.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13288.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13289.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13301.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13321.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13333.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst24.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst26.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst27.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst28.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst31.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst42.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst62.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst80.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst89.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst90.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst96.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst97.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst103.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst105.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst109.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst119.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst128.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst135.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst136.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst142.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst152.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst157.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst163.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst171.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst177.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst198.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst206.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst219.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst222.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst228.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst242.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst251.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst252.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst266.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst295.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst299.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst306.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst314.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst317.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst322.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst334.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst353.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst359.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst396.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst403.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst420.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst421.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst437.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst469.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst472.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst475.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst482.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst498.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst513.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst519.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst547.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst556.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst563.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst568.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst578.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst587.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst598.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst601.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst604.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst610.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst618.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst637.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst657.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst663.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst667.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst698.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst699.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst705.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst715.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst729.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst737.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst759.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst775.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst778.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst784.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst798.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst819.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst820.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst827.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst836.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst843.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst850.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst866.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst873.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst874.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst878.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst880.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst884.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst892.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst934.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst936.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst949.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst969.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst982.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst983.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst986.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst991.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst999.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1018.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1023.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1024.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1028.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1029.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1030.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1031.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1046.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1055.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1056.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1057.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1060.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1079.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1092.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1094.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1106.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1120.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1171.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1183.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1208.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1209.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1227.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1239.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1252.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1253.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1298.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1301.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1302.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1307.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1327.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1342.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1349.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1353.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1355.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1360.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1372.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1421.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1423.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1426.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1454.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1456.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1480.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1506.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1508.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1522.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1529.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1542.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1552.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1564.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1576.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1582.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1616.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1627.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1638.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1644.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1653.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1684.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1689.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1693.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1694.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1722.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1727.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1728.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1737.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1741.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1761.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1767.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1771.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1773.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1779.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1791.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1792.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1817.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1820.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1823.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1824.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1830.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1837.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1847.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1849.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1861.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1884.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1916.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1923.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1929.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1936.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1946.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1953.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1956.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1963.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1989.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2002.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2016.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2024.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2041.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2066.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2088.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2094.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2098.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2102.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2103.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2107.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2110.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2112.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2131.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2133.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2141.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2148.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2153.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2172.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2174.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2185.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2194.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2196.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2205.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2216.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2218.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2220.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2223.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2233.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2240.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2250.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2261.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2263.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2273.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2279.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2283.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2291.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2300.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2312.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2330.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2332.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2338.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2342.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2346.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2360.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2364.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2377.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2385.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2386.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2387.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2393.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2400.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2427.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2430.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2449.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2481.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2482.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2497.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2510.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2511.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2530.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2533.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2538.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2541.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2543.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2593.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2594.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2602.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2604.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2617.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2634.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2661.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2665.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2713.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2718.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2738.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2739.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2741.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2749.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2753.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2758.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2761.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2770.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2789.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2790.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2795.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2824.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2843.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2845.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2870.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2877.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2888.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2918.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2920.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2924.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2963.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2964.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2972.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2995.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3018.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3034.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3054.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3057.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3070.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3076.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3136.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3142.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3145.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3164.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3172.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3180.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3193.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3201.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3203.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3245.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3247.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3256.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3259.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3261.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3298.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3311.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3317.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3318.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3323.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3334.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3336.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3354.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3375.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3376.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3401.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3404.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3408.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3416.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3426.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3428.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3435.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3439.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3455.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3467.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3489.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3503.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3516.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3519.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3526.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3527.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3533.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3536.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3540.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3546.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3547.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3570.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3572.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3595.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3596.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3603.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3605.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3606.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3608.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3612.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3634.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3644.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3657.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3664.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3670.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3690.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3695.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3696.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3718.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3725.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3727.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3749.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3761.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3762.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3769.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3770.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3780.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3784.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3785.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3789.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3847.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3858.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3860.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3866.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3888.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3895.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3900.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3902.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3916.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3923.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3931.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3933.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3947.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3986.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3990.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3994.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4004.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4016.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4026.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4038.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4043.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4060.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4062.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4077.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4085.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4086.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4108.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4132.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4136.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4153.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4155.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4185.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4186.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4187.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4192.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4194.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4198.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4203.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4204.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4219.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4223.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4225.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4248.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4250.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4256.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4274.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4294.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4306.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4310.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4314.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4334.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4381.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4387.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4395.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4400.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4402.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4421.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4422.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4423.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4455.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4470.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4524.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4531.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4539.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4555.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4561.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4569.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4571.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4576.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4582.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4613.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4617.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4666.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4669.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4675.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4686.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4704.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4706.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4745.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4755.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4780.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4784.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4800.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4815.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4816.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4832.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4850.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4855.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4864.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4891.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4895.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4901.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4902.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4916.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4922.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4937.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4946.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4947.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4959.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4974.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4976.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4983.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4992.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4995.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5005.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5020.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5022.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5041.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5042.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5046.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5047.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5114.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5137.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5148.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5160.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5177.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5182.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5185.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5198.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5206.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5230.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5235.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5238.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5265.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5291.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5297.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5311.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5317.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5325.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5330.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5347.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5349.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5365.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5367.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5377.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5390.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5400.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5405.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5418.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5438.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5449.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5469.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5470.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5473.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5488.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5492.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5493.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5499.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5530.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5535.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5547.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5566.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5570.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5576.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5581.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5588.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5592.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5598.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5611.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5635.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5639.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5640.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5644.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5664.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5676.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5678.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5679.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5687.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5707.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5710.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5712.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5714.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5737.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5757.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5762.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5770.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5776.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5779.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5781.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5788.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5797.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5832.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5838.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5856.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5859.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5861.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5864.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5888.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5896.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5900.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5925.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5930.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5940.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5948.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5956.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5987.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5994.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6012.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6049.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6066.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6087.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6108.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6110.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6162.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6169.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6190.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6196.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6224.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6227.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6229.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6235.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6252.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6255.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6264.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6268.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6272.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6273.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6307.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6323.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6332.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6365.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6367.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6368.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6372.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6385.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6387.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6393.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6394.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6396.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6400.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6414.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6421.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6424.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6443.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6459.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6465.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6474.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6476.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6478.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6480.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6481.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6497.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6537.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6538.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6539.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6540.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6541.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6553.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6565.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6590.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6592.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6598.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6600.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6612.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6628.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6630.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6641.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6643.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6649.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6660.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6661.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6668.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6680.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6688.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6701.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6720.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6734.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6735.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6765.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6767.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6780.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6786.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6805.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6811.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6826.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6837.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6839.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6863.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6870.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6877.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6879.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6882.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6883.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6897.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6902.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6910.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6911.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6938.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6942.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6949.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6958.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6962.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6972.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6975.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6976.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6988.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7009.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7010.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7020.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7021.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7026.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7038.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7055.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7060.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7064.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7084.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7085.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7086.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7088.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7091.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7126.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7144.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7160.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7163.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7178.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7187.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7189.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7219.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7226.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7232.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7233.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7242.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7252.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7254.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7264.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7266.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7304.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7355.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7369.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7370.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7371.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7373.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7375.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7382.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7390.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7437.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7442.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7449.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7459.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7471.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7489.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7499.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7529.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7547.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7551.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7597.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7611.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7621.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7643.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7647.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7660.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7661.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7669.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7671.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7684.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7687.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7689.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7695.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7712.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7720.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7729.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7742.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7743.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7745.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7746.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7757.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7759.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7766.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7770.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7809.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7815.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7836.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7865.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7868.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7881.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7899.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7911.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7953.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7958.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7985.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7988.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7996.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7999.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8001.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8012.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8016.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8030.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8032.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8034.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8039.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8058.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8067.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8083.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8086.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8091.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8111.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8128.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8150.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8179.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8182.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8185.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8190.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8200.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8219.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8225.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8230.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8247.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8249.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8256.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8269.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8271.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8280.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8282.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8295.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8301.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8322.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8331.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8332.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8353.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8354.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8356.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8359.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8389.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8395.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8400.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8405.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8420.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8428.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8436.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8439.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8452.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8456.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8457.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8470.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8494.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8512.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8513.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8542.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8551.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8552.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8557.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8573.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8607.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8619.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8623.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8628.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8630.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8642.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8648.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8652.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8660.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8661.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8675.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8705.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8717.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8722.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8732.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8736.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8739.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8774.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8800.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8801.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8802.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8816.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8833.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8839.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8855.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8893.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8898.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8904.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8907.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8914.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8917.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8922.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8932.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8940.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8957.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8979.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9005.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9007.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9016.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9018.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9021.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9026.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9036.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9050.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9060.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9071.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9089.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9098.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9136.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9148.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9152.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9160.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9178.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9180.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9207.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9231.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9260.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9262.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9264.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9267.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9317.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9326.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9335.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9352.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9386.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9398.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9409.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9424.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9437.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9443.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9450.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9452.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9455.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9474.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9475.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9479.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9487.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9498.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9515.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9526.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9529.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9533.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9543.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9544.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9555.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9559.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9593.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9597.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9600.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9620.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9627.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9630.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9631.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9638.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9646.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9648.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9651.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9652.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9673.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9680.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9684.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9709.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9716.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9728.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9730.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9753.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9761.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9764.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9765.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9767.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9769.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9785.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9801.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9813.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9818.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9859.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9869.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9879.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9882.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9885.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9892.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9902.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9927.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9928.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9929.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9934.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9939.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9940.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9941.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9954.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9992.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9999.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10027.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10086.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10087.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10106.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10109.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10143.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10145.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10158.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10177.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10181.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10182.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10191.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10216.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10217.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10221.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10224.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10251.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10260.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10266.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10286.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10291.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10295.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10307.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10318.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10348.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10367.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10372.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10378.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10390.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10393.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10410.xdti_16f_9t_96_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10423.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10436.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10441.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10446.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10459.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10465.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10472.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10473.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10475.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10497.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10500.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10508.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10519.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10521.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10547.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10555.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10562.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10583.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10584.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10599.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10617.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10643.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10655.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10664.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10665.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10673.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10698.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10717.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10726.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10730.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10740.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10751.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10756.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10778.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10803.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10804.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10805.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10818.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10826.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10831.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10840.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10843.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10851.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10867.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10869.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10881.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10900.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10920.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10921.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10925.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10932.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10937.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10939.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10950.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10953.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10957.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10978.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10980.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10982.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10989.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11000.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11003.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11011.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11054.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11059.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11065.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11072.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11081.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11095.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11101.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11111.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11112.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11115.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11124.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11155.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11156.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11163.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11166.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11176.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11190.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11199.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11216.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11217.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11221.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11225.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11250.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11256.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11278.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11289.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11304.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11317.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11380.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11402.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11407.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11431.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11439.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11458.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11464.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11479.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11486.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11500.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11501.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11502.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11509.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11512.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11536.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11581.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11595.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11603.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11643.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11647.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11650.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11662.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11668.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11670.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11691.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11719.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11735.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11762.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11786.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11789.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11806.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11820.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11822.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11833.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11840.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11842.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11858.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11890.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11895.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11922.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11943.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11951.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11978.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11979.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11982.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11992.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12038.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12042.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12079.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12080.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12096.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12117.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12121.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12133.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12135.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12137.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12147.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12149.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12154.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12157.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12195.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12202.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12235.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12236.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12241.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12267.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12278.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12279.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12281.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12286.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12289.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12303.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12306.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12310.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12330.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12343.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12364.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12378.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12403.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12415.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12419.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12442.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12445.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12446.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12449.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12454.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12456.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12466.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12489.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12490.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12497.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12498.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12541.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12567.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12571.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12572.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12581.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12597.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12613.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12638.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12661.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12663.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12696.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12699.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12706.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12738.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12744.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12749.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12750.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12765.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12766.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12772.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12786.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12789.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12796.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12809.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12810.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12813.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12818.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12835.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12876.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12883.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12900.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12907.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12916.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12928.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12946.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12962.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12970.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12982.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12983.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12998.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13034.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13037.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13061.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13070.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13072.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13089.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13101.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13118.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13131.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13139.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13141.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13157.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13178.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13180.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13187.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13191.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13194.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13201.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13202.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13211.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13231.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13238.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13249.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13253.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13259.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13281.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13288.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13289.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13301.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13321.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13333.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst24.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst26.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst27.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst28.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst31.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst42.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst62.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst80.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst89.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst90.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst96.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst97.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst103.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst105.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst109.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst119.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst128.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst135.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst136.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst142.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst152.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst157.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst163.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst171.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst177.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst198.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst206.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst219.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst222.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst228.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst242.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst251.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst252.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst266.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst295.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst299.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst306.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst314.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst317.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst322.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst334.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst353.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst359.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst396.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst403.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst420.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst421.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst437.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst469.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst472.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst475.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst482.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst498.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst513.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst519.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst547.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst556.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst563.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst568.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst578.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst587.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst598.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst601.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst604.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst610.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst618.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst637.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst657.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst663.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst667.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst698.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst699.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst705.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst715.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst729.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst737.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst759.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst775.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst778.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst784.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst798.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst819.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst820.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst827.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst836.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst843.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst850.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst866.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst873.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst874.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst878.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst880.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst884.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst892.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst934.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst936.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst949.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst969.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst982.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst983.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst986.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst991.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst999.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1018.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1023.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1024.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1028.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1029.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1030.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1031.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1046.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1055.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1056.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1057.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1060.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1079.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1092.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1094.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1106.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1120.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1171.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1183.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1208.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1209.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1227.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1239.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1252.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1253.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1298.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1301.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1302.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1307.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1327.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1342.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1349.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1353.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1355.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1360.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1372.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1421.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1423.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1426.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1454.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1456.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1480.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1506.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1508.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1522.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1529.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1542.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1552.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1564.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1576.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1582.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1616.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1627.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1638.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1644.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1653.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1684.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1689.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1693.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1694.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1722.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1727.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1728.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1737.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1741.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1761.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1767.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1771.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1773.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1779.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1791.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1792.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1817.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1820.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1823.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1824.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1830.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1837.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1847.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1849.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1861.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1884.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1916.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1923.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1929.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1936.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1946.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1953.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1956.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1963.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1989.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2002.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2016.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2024.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2041.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2066.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2088.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2094.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2098.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2102.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2103.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2107.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2110.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2112.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2131.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2133.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2141.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2148.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2153.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2172.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2174.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2185.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2194.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2196.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2205.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2216.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2218.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2220.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2223.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2233.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2240.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2250.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2261.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2263.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2273.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2279.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2283.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2291.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2300.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2312.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2330.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2332.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2338.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2342.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2346.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2360.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2364.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2377.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2385.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2386.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2387.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2393.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2400.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2427.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2430.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2449.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2481.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2482.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2497.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2510.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2511.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2530.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2533.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2538.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2541.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2543.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2593.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2594.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2602.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2604.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2617.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2634.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2661.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2665.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2713.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2718.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2738.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2739.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2741.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2749.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2753.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2758.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2761.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2770.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2789.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2790.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2795.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2824.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2843.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2845.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2870.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2877.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2888.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2918.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2920.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2924.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2963.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2964.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2972.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2995.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3018.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3034.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3054.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3057.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3070.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3076.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3136.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3142.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3145.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3164.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3172.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3180.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3193.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3201.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3203.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3245.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3247.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3256.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3259.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3261.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3298.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3311.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3317.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3318.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3323.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3334.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3336.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3354.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3375.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3376.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3401.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3404.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3408.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3416.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3426.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3428.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3435.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3439.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3455.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3467.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3489.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3503.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3516.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3519.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3526.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3527.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3533.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3536.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3540.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3546.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3547.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3570.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3572.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3595.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3596.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3603.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3605.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3606.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3608.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3612.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3634.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3644.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3657.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3664.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3670.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3690.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3695.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3696.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3718.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3725.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3727.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3749.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3761.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3762.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3769.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3770.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3780.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3784.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3785.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3789.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3847.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3858.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3860.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3866.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3888.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3895.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3900.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3902.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3916.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3923.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3931.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3933.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3947.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3986.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3990.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3994.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4004.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4016.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4026.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4038.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4043.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4060.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4062.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4077.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4085.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4086.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4108.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4132.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4136.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4153.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4155.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4185.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4186.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4187.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4192.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4194.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4198.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4203.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4204.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4219.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4223.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4225.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4248.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4250.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4256.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4274.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4294.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4306.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4310.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4314.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4334.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4381.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4387.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4395.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4400.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4402.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4421.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4422.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4423.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4455.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4470.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4524.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4531.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4539.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4555.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4561.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4569.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4571.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4576.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4582.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4613.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4617.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4666.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4669.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4675.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4686.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4704.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4706.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4745.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4755.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4780.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4784.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4800.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4815.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4816.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4832.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4850.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4855.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4864.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4891.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4895.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4901.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4902.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4916.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4922.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4937.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4946.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4947.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4959.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4974.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4976.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4983.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4992.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4995.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5005.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5020.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5022.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5041.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5042.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5046.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5047.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5114.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5137.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5148.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5160.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5177.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5182.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5185.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5198.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5206.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5230.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5235.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5238.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5265.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5291.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5297.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5311.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5317.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5325.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5330.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5347.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5349.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5365.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5367.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5377.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5390.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5400.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5405.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5418.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5438.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5449.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5469.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5470.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5473.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5488.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5492.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5493.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5499.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5530.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5535.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5547.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5566.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5570.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5576.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5581.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5588.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5592.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5598.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5611.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5635.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5639.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5640.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5644.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5664.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5676.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5678.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5679.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5687.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5707.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5710.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5712.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5714.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5737.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5757.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5762.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5770.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5776.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5779.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5781.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5788.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5797.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5832.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5838.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5856.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5859.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5861.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5864.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5888.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5896.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5900.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5925.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5930.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5940.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5948.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5956.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5987.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5994.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6012.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6049.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6066.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6087.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6108.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6110.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6162.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6169.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6190.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6196.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6224.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6227.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6229.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6235.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6252.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6255.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6264.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6268.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6272.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6273.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6307.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6323.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6332.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6365.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6367.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6368.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6372.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6385.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6387.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6393.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6394.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6396.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6400.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6414.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6421.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6424.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6443.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6459.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6465.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6474.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6476.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6478.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6480.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6481.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6497.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6537.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6538.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6539.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6540.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6541.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6553.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6565.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6590.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6592.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6598.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6600.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6612.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6628.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6630.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6641.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6643.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6649.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6660.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6661.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6668.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6680.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6688.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6701.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6720.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6734.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6735.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6765.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6767.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6780.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6786.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6805.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6811.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6826.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6837.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6839.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6863.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6870.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6877.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6879.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6882.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6883.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6897.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6902.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6910.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6911.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6938.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6942.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6949.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6958.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6962.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6972.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6975.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6976.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6988.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7009.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7010.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7020.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7021.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7026.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7038.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7055.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7060.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7064.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7084.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7085.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7086.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7088.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7091.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7126.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7144.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7160.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7163.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7178.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7187.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7189.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7219.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7226.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7232.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7233.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7242.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7252.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7254.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7264.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7266.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7304.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7355.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7369.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7370.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7371.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7373.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7375.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7382.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7390.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7437.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7442.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7449.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7459.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7471.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7489.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7499.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7529.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7547.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7551.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7597.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7611.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7621.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7643.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7647.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7660.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7661.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7669.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7671.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7684.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7687.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7689.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7695.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7712.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7720.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7729.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7742.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7743.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7745.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7746.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7757.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7759.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7766.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7770.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7809.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7815.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7836.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7865.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7868.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7881.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7899.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7911.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7953.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7958.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7985.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7988.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7996.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7999.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8001.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8012.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8016.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8030.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8032.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8034.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8039.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8058.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8067.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8083.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8086.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8091.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8111.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8128.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8150.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8179.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8182.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8185.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8190.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8200.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8219.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8225.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8230.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8247.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8249.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8256.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8269.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8271.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8280.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8282.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8295.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8301.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8322.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8331.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8332.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8353.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8354.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8356.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8359.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8389.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8395.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8400.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8405.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8420.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8428.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8436.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8439.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8452.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8456.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8457.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8470.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8494.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8512.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8513.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8542.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8551.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8552.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8557.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8573.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8607.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8619.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8623.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8628.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8630.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8642.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8648.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8652.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8660.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8661.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8675.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8705.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8717.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8722.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8732.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8736.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8739.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8774.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8800.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8801.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8802.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8816.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8833.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8839.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8855.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8893.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8898.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8904.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8907.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8914.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8917.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8922.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8932.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8940.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8957.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8979.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9005.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9007.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9016.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9018.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9021.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9026.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9036.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9050.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9060.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9071.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9089.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9098.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9136.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9148.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9152.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9160.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9178.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9180.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9207.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9231.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9260.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9262.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9264.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9267.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9317.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9326.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9335.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9352.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9386.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9398.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9409.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9424.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9437.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9443.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9450.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9452.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9455.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9474.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9475.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9479.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9487.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9498.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9515.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9526.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9529.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9533.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9543.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9544.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9555.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9559.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9593.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9597.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9600.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9620.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9627.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9630.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9631.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9638.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9646.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9648.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9651.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9652.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9673.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9680.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9684.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9709.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9716.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9728.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9730.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9753.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9761.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9764.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9765.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9767.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9769.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9785.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9801.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9813.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9818.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9859.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9869.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9879.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9882.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9885.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9892.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9902.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9927.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9928.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9929.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9934.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9939.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9940.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9941.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9954.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9992.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9999.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10027.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10086.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10087.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10106.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10109.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10143.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10145.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10158.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10177.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10181.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10182.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10191.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10216.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10217.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10221.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10224.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10251.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10260.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10266.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10286.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10291.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10295.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10307.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10318.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10348.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10367.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10372.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10378.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10390.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10393.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10410.xdti_16f_9t_96_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10423.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10436.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10441.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10446.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10459.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10465.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10472.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10473.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10475.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10497.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10500.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10508.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10519.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10521.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10547.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10555.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10562.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10583.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10584.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10599.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10617.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10643.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10655.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10664.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10665.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10673.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10698.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10717.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10726.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10730.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10740.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10751.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10756.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10778.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10803.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10804.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10805.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10818.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10826.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10831.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10840.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10843.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10851.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10867.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10869.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10881.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10900.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10920.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10921.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10925.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10932.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10937.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10939.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10950.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10953.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10957.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10978.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10980.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10982.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10989.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11000.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11003.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11011.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11054.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11059.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11065.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11072.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11081.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11095.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11101.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11111.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11112.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11115.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11124.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11155.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11156.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11163.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11166.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11176.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11190.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11199.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11216.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11217.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11221.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11225.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11250.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11256.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11278.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11289.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11304.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11317.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11380.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11402.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11407.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11431.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11439.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11458.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11464.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11479.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11486.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11500.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11501.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11502.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11509.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11512.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11536.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11581.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11595.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11603.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11643.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11647.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11650.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11662.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11668.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11670.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11691.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11719.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11735.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11762.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11786.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11789.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11806.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11820.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11822.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11833.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11840.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11842.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11858.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11890.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11895.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11922.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11943.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11951.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11978.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11979.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11982.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11992.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12038.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12042.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12079.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12080.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12096.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12117.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12121.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12133.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12135.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12137.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12147.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12149.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12154.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12157.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12195.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12202.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12235.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12236.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12241.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12267.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12278.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12279.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12281.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12286.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12289.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12303.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12306.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12310.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12330.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12343.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12364.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12378.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12403.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12415.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12419.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12442.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12445.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12446.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12449.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12454.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12456.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12466.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12489.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12490.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12497.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12498.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12541.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12567.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12571.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12572.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12581.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12597.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12613.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12638.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12661.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12663.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12696.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12699.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12706.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12738.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12744.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12749.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12750.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12765.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12766.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12772.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12786.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12789.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12796.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12809.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12810.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12813.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12818.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12835.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12876.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12883.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12900.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12907.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12916.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12928.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12946.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12962.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12970.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12982.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12983.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12998.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13034.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13037.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13061.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13070.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13072.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13089.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13101.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13118.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13131.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13139.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13141.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13157.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13178.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13180.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13187.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13191.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13194.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13201.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13202.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13211.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13231.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13238.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13249.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13253.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13259.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13281.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13288.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13289.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13301.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13321.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13333.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst24.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst26.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst27.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst28.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst31.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst42.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst62.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst80.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst89.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst90.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst96.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst97.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst103.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst105.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst109.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst119.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst128.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst135.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst136.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst142.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst152.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst157.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst163.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst171.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst177.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst198.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst206.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst219.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst222.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst228.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst242.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst251.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst252.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst266.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst295.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst299.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst306.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst314.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst317.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst322.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst334.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst353.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst359.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst396.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst403.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst420.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst421.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst437.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst469.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst472.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst475.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst482.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst498.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst513.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst519.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst547.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst556.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst563.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst568.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst578.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst587.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst598.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst601.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst604.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst610.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst618.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst637.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst657.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst663.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst667.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst698.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst699.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst705.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst715.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst729.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst737.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst759.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst775.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst778.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst784.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst798.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst819.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst820.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst827.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst836.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst843.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst850.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst866.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst873.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst874.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst878.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst880.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst884.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst892.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst934.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst936.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst949.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst969.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst982.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst983.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst986.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst991.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst999.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1018.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1023.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1024.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1028.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1029.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1030.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1031.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1046.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1055.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1056.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1057.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1060.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1079.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1092.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1094.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1106.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1120.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1171.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1183.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1208.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1209.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1227.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1239.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1252.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1253.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1298.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1301.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1302.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1307.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1327.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1342.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1349.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1353.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1355.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1360.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1372.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1421.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1423.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1426.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1454.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1456.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1480.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1506.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1508.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1522.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1529.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1542.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1552.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1564.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1576.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1582.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1616.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1627.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1638.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1644.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1653.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1684.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1689.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1693.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1694.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1722.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1727.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1728.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1737.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1741.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1761.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1767.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1771.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1773.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1779.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1791.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1792.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1817.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1820.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1823.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1824.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1830.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1837.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1847.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1849.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1861.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1884.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1916.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1923.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1929.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1936.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1946.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1953.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1956.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1963.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1989.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2002.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2016.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2024.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2041.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2066.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2088.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2094.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2098.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2102.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2103.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2107.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2110.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2112.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2131.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2133.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2141.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2148.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2153.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2172.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2174.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2185.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2194.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2196.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2205.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2216.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2218.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2220.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2223.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2233.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2240.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2250.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2261.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2263.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2273.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2279.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2283.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2291.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2300.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2312.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2330.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2332.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2338.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2342.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2346.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2360.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2364.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2377.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2385.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2386.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2387.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2393.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2400.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2427.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2430.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2449.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2481.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2482.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2497.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2510.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2511.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2530.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2533.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2538.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2541.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2543.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2593.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2594.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2602.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2604.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2617.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2634.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2661.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2665.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2713.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2718.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2738.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2739.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2741.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2749.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2753.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2758.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2761.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2770.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2789.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2790.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2795.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2824.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2843.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2845.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2870.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2877.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2888.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2918.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2920.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2924.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2963.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2964.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2972.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2995.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3018.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3034.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3054.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3057.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3070.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3076.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3136.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3142.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3145.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3164.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3172.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3180.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3193.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3201.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3203.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3245.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3247.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3256.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3259.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3261.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3298.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3311.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3317.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3318.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3323.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3334.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3336.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3354.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3375.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3376.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3401.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3404.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3408.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3416.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3426.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3428.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3435.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3439.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3455.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3467.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3489.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3503.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3516.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3519.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3526.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3527.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3533.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3536.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3540.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3546.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3547.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3570.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3572.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3595.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3596.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3603.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3605.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3606.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3608.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3612.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3634.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3644.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3657.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3664.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3670.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3690.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3695.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3696.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3718.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3725.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3727.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3749.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3761.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3762.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3769.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3770.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3780.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3784.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3785.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3789.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3847.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3858.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3860.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3866.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3888.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3895.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3900.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3902.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3916.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3923.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3931.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3933.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3947.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3986.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3990.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3994.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4004.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4016.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4026.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4038.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4043.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4060.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4062.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4077.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4085.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4086.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4108.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4132.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4136.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4153.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4155.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4185.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4186.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4187.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4192.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4194.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4198.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4203.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4204.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4219.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4223.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4225.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4248.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4250.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4256.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4274.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4294.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4306.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4310.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4314.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4334.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4381.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4387.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4395.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4400.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4402.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4421.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4422.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4423.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4455.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4470.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4524.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4531.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4539.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4555.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4561.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4569.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4571.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4576.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4582.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4613.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4617.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4649.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4666.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4669.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4675.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4686.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4704.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4706.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4745.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4755.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4780.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4784.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4800.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4815.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4816.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4832.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4850.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4855.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4864.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4891.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4895.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4901.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4902.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4916.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4922.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4937.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4946.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4947.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4959.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4974.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4976.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4983.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4992.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4995.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5005.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5020.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5022.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5041.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5042.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5046.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5047.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5114.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5137.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5148.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5160.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5177.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5182.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5185.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5198.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5206.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5230.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5235.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5238.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5265.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5291.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5297.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5311.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5317.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5325.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5330.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5347.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5349.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5365.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5367.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5377.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5390.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5400.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5405.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5418.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5438.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5449.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5469.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5470.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5473.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5488.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5492.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5493.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5499.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5530.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5535.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5547.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5566.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5570.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5576.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5581.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5588.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5592.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5598.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5611.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5635.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5639.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5640.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5644.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5664.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5676.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5678.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5679.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5687.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5707.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5710.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5712.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5714.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5737.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5757.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5762.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5770.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5776.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5779.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5781.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5788.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5797.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5832.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5838.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5856.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5859.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5861.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5864.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5888.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5896.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5900.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5925.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5930.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5940.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5948.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5956.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5987.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5994.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6012.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6049.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6066.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6087.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6108.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6110.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6162.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6169.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6190.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6196.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6224.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6227.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6229.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6235.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6252.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6255.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6264.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6268.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6272.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6273.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6307.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6323.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6332.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6365.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6367.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6368.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6372.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6385.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6387.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6393.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6394.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6396.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6400.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6414.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6421.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6424.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6443.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6459.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6465.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6474.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6476.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6478.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6480.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6481.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6497.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6537.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6538.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6539.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6540.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6541.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6553.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6565.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6590.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6592.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6598.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6600.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6612.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6628.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6630.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6641.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6643.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6649.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6660.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6661.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6668.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6680.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6688.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6701.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6720.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6734.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6735.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6765.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6767.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6780.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6786.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6805.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6811.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6826.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6837.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6839.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6854.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6863.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6870.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6877.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6879.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6882.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6883.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6897.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6902.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6910.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6911.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6938.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6942.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6949.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6958.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6962.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6972.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6975.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6976.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6988.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7009.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7010.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7020.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7021.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7026.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7038.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7055.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7060.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7064.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7084.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7085.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7086.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7088.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7091.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7126.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7144.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7160.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7163.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7178.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7187.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7189.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7219.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7226.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7232.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7233.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7242.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7252.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7254.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7264.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7266.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7304.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7355.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7369.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7370.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7371.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7373.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7375.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7382.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7390.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7437.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7442.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7449.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7459.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7471.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7489.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7499.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7529.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7547.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7551.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7597.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7611.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7621.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7643.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7647.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7660.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7661.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7669.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7671.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7684.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7687.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7689.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7695.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7712.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7720.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7729.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7742.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7743.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7745.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7746.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7757.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7759.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7766.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7770.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7809.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7815.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7836.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7865.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7868.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7881.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7899.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7911.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7953.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7958.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7985.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7988.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7996.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7999.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8001.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8012.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8016.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8030.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8032.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8034.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8039.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8058.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8067.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8083.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8086.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8091.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8111.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8128.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8150.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8179.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8182.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8185.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8190.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8200.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8219.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8225.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8230.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8247.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8249.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8256.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8269.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8271.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8280.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8282.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8295.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8301.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8322.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8331.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8332.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8353.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8354.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8356.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8359.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8389.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8395.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8400.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8405.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8420.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8428.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8436.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8439.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8452.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8456.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8457.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8470.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8494.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8512.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8513.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8542.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8551.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8552.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8557.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8573.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8607.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8619.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8623.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8628.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8630.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8642.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8648.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8652.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8660.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8661.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8675.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8705.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8717.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8722.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8732.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8736.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8739.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8774.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8800.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8801.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8802.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8816.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8833.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8839.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8855.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8893.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8898.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8904.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8907.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8914.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8917.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8922.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8932.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8940.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8957.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8979.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9005.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9007.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9016.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9018.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9021.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9026.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9036.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9050.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9060.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9071.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9089.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9098.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9136.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9148.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9152.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9160.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9178.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9180.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9207.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9231.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9260.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9262.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9264.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9267.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9317.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9326.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9335.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9352.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9386.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9398.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9409.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9424.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9437.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9443.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9450.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9452.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9455.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9474.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9475.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9479.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9487.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9498.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9515.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9526.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9529.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9533.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9543.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9544.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9555.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9559.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9593.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9597.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9600.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9620.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9627.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9630.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9631.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9638.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9646.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9648.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9651.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9652.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9673.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9680.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9684.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9709.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9716.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9728.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9730.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9753.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9761.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9764.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9765.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9767.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9769.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9785.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9801.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9813.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9818.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9859.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9869.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9879.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9882.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9885.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9892.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9902.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9927.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9928.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9929.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9934.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9939.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9940.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9941.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9954.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9992.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9999.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10027.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10086.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10087.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10106.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10109.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10143.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10145.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10158.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10177.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10181.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10182.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10191.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10216.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10217.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10221.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10224.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10251.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10260.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10266.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10286.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10291.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10295.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10307.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10318.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10348.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10367.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10372.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10378.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10390.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10393.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10410.xdti_16f_9t_96_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10423.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10436.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10441.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10446.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10459.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10465.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10472.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10473.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10475.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10497.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10500.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10508.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10519.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10521.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10547.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10555.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10562.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10583.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10584.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10599.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10617.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10643.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10655.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10664.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10665.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10673.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10698.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10717.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10726.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10730.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10740.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10751.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10756.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10778.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10803.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10804.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10805.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10818.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10826.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10831.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10840.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10843.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10851.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10867.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10869.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10881.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10900.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10920.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10921.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10925.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10932.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10937.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10939.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10950.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10953.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10957.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10978.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10980.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10982.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10989.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11000.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11003.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11011.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11054.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11059.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11065.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11072.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11081.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11095.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11101.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11111.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11112.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11115.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11124.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11155.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11156.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11163.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11166.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11176.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11190.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11199.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11216.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11217.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11221.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11225.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11250.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11256.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11278.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11289.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11304.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11317.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11380.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11402.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11407.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11431.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11439.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11458.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11464.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11479.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11486.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11500.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11501.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11502.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11509.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11512.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11536.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11549.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11581.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11595.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11603.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11643.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11647.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11650.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11662.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11668.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11670.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11691.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11719.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11735.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11762.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11786.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11789.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11806.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11820.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11822.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11833.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11840.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11842.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11858.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11890.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11895.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11922.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11943.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11951.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11978.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11979.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11982.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11992.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12038.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12042.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12076.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12079.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12080.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12096.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12117.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12121.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12133.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12135.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12137.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12147.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12149.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12154.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12157.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12195.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12202.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12235.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12236.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12241.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12267.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12278.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12279.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12281.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12286.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12289.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12303.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12306.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12310.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12330.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12343.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12364.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12378.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12403.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12415.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12419.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12442.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12445.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12446.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12449.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12454.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12456.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12466.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12489.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12490.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12497.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12498.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12541.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12567.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12571.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12572.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12581.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12589.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12597.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12613.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12638.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12661.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12663.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12696.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12699.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12706.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12738.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12744.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12749.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12750.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12765.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12766.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12772.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12786.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12789.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12796.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12809.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12810.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12813.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12818.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12835.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12876.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12883.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12900.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12907.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12916.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12928.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12946.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12962.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12970.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12982.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12983.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12998.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13034.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13037.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13061.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13070.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13072.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13089.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13101.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13118.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13131.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13139.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13141.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13157.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13178.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13180.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13187.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13191.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13194.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13201.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13202.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13211.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13231.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13238.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13249.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13253.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13259.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13281.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13288.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13289.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13301.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13321.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13333.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00

Cond Coverage for Module : dti_mux21
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       7930
 EXPRESSION (S ? D1 : D0)
             1
-1-Status
0Covered
1Covered
Toggle Coverage for Module : dti_mux21
TotalCoveredPercent
Totals 6 4 66.67
Total Bits 12 8 66.67
Total Bits 0->1 6 4 66.67
Total Bits 1->0 6 4 66.67

Ports 6 4 66.67
Port Bits 12 8 66.67
Port Bits 0->1 6 4 66.67
Port Bits 1->0 6 4 66.67

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
VDD No No No INPUT
VSS No No No INPUT
Z Yes Yes Yes OUTPUT
D0 Yes Yes Yes INPUT
D1 Yes Yes Yes INPUT
S Yes Yes Yes INPUT

Branch Coverage for Module : dti_mux21
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 7930 2 2 100.00 



7930       assign Z = S ? D1 : D0;
                        -1-  
                        ==>  
                        ==>

Branches:
-1-Status
1 Covered
0 Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%